1. Field of the Invention
The present invention relates to a semiconductor device using an SOI substrate having an SOI (Silicon On Insulator) structure in which a buried oxidation film and a surface silicon layer are provided on a support substrate made of silicon and a method of fabricating the same.
2. Description of the Related Art
The SOI substrate is a semiconductor substrate where a surface silicon layer is formed above a support substrate made of silicon with a buried oxidation film therebetween. The semiconductor device fabricated using such SOI substrate has a lot of advantages compared with a semiconductor device fabricated with bulk silicon. For instance, these advantages are that the semiconductor device with the SOI substrate has high resistance to temperature and radiation, capability of realizing quick operation with ease, low power consumption, and so on.
Hereinafter, an example of a semiconductor device using a conventional SOI substrate will be described with FIG. 13.
FIG. 13 is a sectional view showing the enlarged principal portion of an IC chip that is the semiconductor device using the conventional SOI substrate.
In an SOI substrate 1, a buried oxidation film 19 is provided on a support substrate 17 made of silicon and a surface silicon layer is provided on the buried oxidation film 19. However, in FIG. 13, the surface silicon layer is etched to form a plurality of island-shaped component regions and impurities are implanted into each component region and diffused to form a lightly doped P region 3 and a lightly doped N region 4.
An N channel field effect transistor (hereinafter referred to as xe2x80x9can N channel FETxe2x80x9d) 20 and a P channel field effect transistor (hereinafter referred to as xe2x80x9ca P channel FETxe2x80x9d) 30 are provided respectively on the lightly doped P region 3 and the lightly doped N region 4 isolated from each other by an insulating film 23.
In the N channel FET 20, a gate electrode 21 is formed above the center of the lightly doped P region 3 with a gate oxidation film 15 therebetween, and an N source region 7 and an N drain region 5 are formed respectively on both sides of the gate electrode 21. The gate electrode 21, the N source region 7, and the N drain region 5 are respectively provided with metal electrodes (interconnection electrodes) 11 electrically connected thereto and extending onto the insulating film 23 through contact holes 31.
In the P channel FET 30, a gate electrode 21 is formed above the center of the lightly doped N region 4 with a gate oxidation film 15 therebetween, and a P source region 27 and a P drain region 25 are formed respectively on both sides of the gate electrode 21. The gate electrode 21, the P source region 27, and the P drain region 25 are also respectively provided with metal electrodes (interconnection electrodes) 11 electrically connected thereto and extending onto the insulating film 23 through contact holes 31.
Incidentally, since the metal electrodes (interconnection electrodes) connecting with the gate electrodes 21 of the N channel FET 20 and the P channel FET 30 are respectively provided at positions in a section different from FIG. 13, they are not shown in FIG. 13. Moreover, pad portions for providing input/output terminals are formed at the metal electrodes 11 connecting with the outside out of a number of metal electrodes 11, though the illustration thereof is omitted.
The N channel FET 20 and the P channel FET 30 are merely inverse in conduction type of the lightly doped region, the source region, and the drain region, and they have a common basic structure. The pair of N channel FET 20 and P channel FET 30 constitute a CMOS transistor.
In FIG. 13, only one pair of CMOS transistors is shown, but a number of CMOS transistors, other FETs, bipolar transistors, resistors, or capacitors are provided in an actual IC chip. All of these are, of course, made by the SOI technology.
When the IC chip which is the semiconductor device using the aforesaid SOI substrate is operated, it is necessary to ground or bias the support substrate at a predetermined voltage. Thereby, the operation of the IC chip can be stabilized.
However, in the case where the IC chip in which the CMOS transistor is formed on the SOI substrate as shown in FIG. 13 is driven, the support substrate 17 made of silicon is grounded or biased, which causes the following disadvantage.
In one of the FETs composing the CMOS transistor, the support substrate 17 comes to be different in potential from the lightly doped P region 3 or the lightly doped N region 4 which are formed out of the surface silicon layer. For instance, as shown in FIG. 13, when the support substrate is set at the ground potential, the lightly doped P region 3 of the N channel FET 20 is set at the ground potential but the lightly doped N region 4 of the P channel FET 30 must be set at a power source potential (by an applied voltage VDD). Therefore, a potential difference is caused between the lightly doped N region 4 and the support substrate 17.
So, the disadvantage due to an occurrence of such potential difference will be explained with reference to FIG. 14 and FIG. 15 showing an enlarged portion of only one P channel FET 30 in FIG. 13. Incidentally, in the sectional views, part of the hatching is omitted for convenience of illustration.
The lightly doped N region 4 and the P source region 27 in FIG. 14 form a PN junction, normally the P source region 27 is set at the power source potential, and carriers come into recombination in the lightly doped N region 4 near a boundary surface between the lightly doped N region 4 and the P source region 27, whereby a depletion layer 34 is formed as shown in the drawing.
If the value of the voltage VDD applied to the lightly doped region 4 is changed to the positive voltage side, electrons in the lightly doped N region 4 near a boundary surface 39 between the lightly doped N region 4 and the buried oxidation side 19 are excluded, whereby a depletion layer 35 is formed. When the applied voltage VDD becomes about 5V, an inversion layer 36 composed of holes is formed near the boundary surface 39 and the depletion layer 35 growing from the buried oxidation 19 side and the depletion layer 34 growing from the P source region 27 are joined finally.
At this time, the potential difference between the support substrate 17 and the lightly doped N region 4 comes to directly exert on the PN junction formed at the boundary surface between the lightly doped N region 4 and the P source region 27, and thus the potential barrier of the PN junction is lowered, whereby carriers (holes) 37 are supplied from the P source region 27 to the inversion layer 36 as shown by an arrow a in FIG. 15.
On the other hand, since the P drain region 25 is normally applied with a drain voltage Vd with which the P drain region 25 is reverse-biased in relation to the lightly doped N region 4, the carriers (holes) 37 flow from the inversion layer 36 into the P drain region 25 as shown by an arrow c. Consequently, a leakage current appears along the boundary surface 39 as shown by an arrow b, resulting in the formation of a path of current in addition to the channel current. When the leakage current appears as described above, a current flows even when no voltage is applied to the gate electrode 21, whereby the current flowing in the channel cannot be controlled accurately by the voltage applied to the gate electrode 21.
In other words, there is a disadvantage that a leakage current flowing along the boundary surface 39 between the lightly doped N region 4 and the buried oxidation film 19 appears due to the potential difference between the voltage VDD applied to the lightly doped N region 4 and the support substrate 17, resulting in inaccurate control of the channel current.
It is possible that the above disadvantage arises not only in the P channel FET 30 but also in the N channel FET 20. In the case of the N channel FET 20 shown in FIG. 13, there is no potential difference between the lightly doped P region 3 and the support substrate 17 by grounding the lightly doped P region 3, and thus there appears no leakage current in the lightly doped P region 3 at the boundary surface between the lightly doped P region 3 and the buried oxidation film 19.
However, when the voltage VDD is applied to the support substrate 17, though no leakage current appears since the same voltage VDD is applied to the lightly doped N region 4 of the P channel FET 30, the lightly doped P region 3 of the N channel FET 20 needs to be set at the ground potential, which causes a potential difference between the lightly doped P region 3 and the support substrate 17, resulting in appearance of a leakage current.
Consequently, the aforesaid disadvantage due to the leakage current arises in any one of the N channel FET 20 and the P channel FET 30 which compose the CMOS transistor on the SOI substrate.
Moreover, not limited to the CMOS transistor, the same disadvantage arises in a semiconductor device in which N channel FETs and P channel FETs are provided in a mixed manner on an SOI substrate.
The present invention is made to solve the above disadvantage which arises at the time when the semiconductor device (IC chip) using the SOI substrate is used, and an object thereof is to prevent occurrence of a leakage current in the semiconductor device regardless of a voltage applied to a support substrate made of silicon so as to accurately control a channel current.
In order to attain the above object, the semiconductor device according to the present invention is characterized in a semiconductor device in which a field effect transistor is formed on an SOI substrate provided with a surface silicon layer above a support substrate made of silicon with a buried oxidation film therebetween, wherein a lightly doped region of N-type or P-type isolated from one component region and another is formed out of the surface silicon layer of the SOI substrate; a gate electrode is provided above the lightly doped region with a gate oxidation film therebetween, a drain region and a source region made by making the lightly doped region on the front face side different in conduction type from the lightly doped region are provided respectively on both sides of the gate electrode; and a leakage stopping layer which is the same in conduction type as the lightly doped region and higher in impurity concentration than the lightly doped region is provided between the source region and the buried oxidation film.
Since the impurity concentration of the leakage stopping layer provided between the source region and the buried oxidation film is higher than that of the lightly doped region N-type of P-type in the semiconductor device structured as described above, even if there is a potential difference between the support substrate of silicon and the lightly doped region, a depletion layer between the source region and the buried oxidation film becomes hard to grow, whereby the joining together of the depletion layer on the source region side and the depletion layer on the buried oxidation film side is avoided. Therefore, even if an inversion layer occurs in the lightly doped region near the boundary surface between the lightly doped region and the buried oxidation film due to the above potential difference, carriers are not supplied from the source region into the inversion layer, resulting in no flow of leakage current.
Moreover, it is suitable that the leakage stopping layer is provided within an area, which contacts the buried oxidation film and does not contact the source region, in the lightly doped region, or within an area, which contacts neither the source region nor the buried oxidation film, in the lightly doped region.
It is preferable that the leakage stopping layer is thus provided away from the gate electrode, which exerts less influence on the control characteristic of the channel current by the gate voltage.
The fabricating method of a semiconductor device according to the present invention is characterized in a fabricating method of a semiconductor device in which a field effect transistor is formed on an SOI substrate, comprising the steps of:
preparing the SOI substrate provided with a surface silicon layer above a support substrate made of silicon with a buried oxidation film therebetween and selectively etching the surface silicon layer to form a lightly doped region of N-type or P-type isolated from one component region and another;
selectively ion-implanting impurities which are the same in conduction type as the lightly doped region into a portion which will be a source region in the lightly doped region to form a leakage stopping layer;
performing oxidation treatment for the front face of the lightly doped region to form a gate oxidation film;
forming a gate electrode on the gate oxidation film; and
selectively ion-implanting impurities which are different in conduction type from the lightly doped region into the lightly doped region on both sides of the gate electrode and the leakage stopping layer to form a drain region and a source region.
A more complete semiconductor device can be fabricated by further comprising the steps of:
after the step of forming the drain region and the source region,
forming an insulating film on the entire face of the SOI substrate which has been subjected to the aforesaid steps;
performing photo etching treatment for the insulating film to form contact holes at positions in the insulating film which individually correspond to the gate electrode, the drain region, and the source region; and
forming a metal electrode layer on the entire face of the insulating film and in all the contact holes and thereafter performing photo etching treatment to form metal electrodes individually connecting to the gate electrode, the drain region, and the source region separately in the respective contact holes.
The above and other objects, features and advantages of the invention will be apparent from the following detailed description which is to be read in conjunction with the accompanying drawings.